Chiplogic provides/offers full turn-key solutions and ODC services including, Specification, Architecture, RTL Design, Design Verification, Physical Design , DFT and Analog/Mixed Signal services. We have a proven flows and methodologies with hands-on experience and expertise on leading EDA tools and techniques.
With an increasing complexity of multi-million gate System-On- Chip (SoC) designs, aggressive time- to-market windows are becoming tough to meet. ChipLogic Semi has the much-needed expertise and strength to complete your SoC designs successfully while meeting your deadlines. ChipLogic Semi engineers have extensive and in-depth experience in dealing with critical design issues using advanced technologies and have taped-out several low power, multi-voltage domain and complex multi-million SoCs. We add value to the designs of our customers by leveraging systems knowledge and expertise.
Our Design Services offerings
Development of architecture at macro and micro level.
Implementation of RTL using Verilog/ VHDL/ System Verilog.
Synthesis of RTL for SOC/ ASIC/ FPGA/ IP's.
Synthesizable, configurable RTL code in Verilog HDL
UVM based testbench to demonstrate functionality of IP
Reports – Verification, Coverage, STA
Our Key benefits
Lower rate of failure or re-spin
Reduced time to market.
Remarkable improvement in development productivity.
Chiplogic engineers have grown up with the verification techniques and advanced methodologies. We provide Verification services in Digital, Analog and Mixed signal areas. We enable you to rapidly build verification environment to achieve your design and verification targets through its unique blend of innovative tools and technologies. Our verification methodology helps to build highly layered, scalable, reusable, and extensible verification environments for module, IP, Subsystem and SoC level verification, providing maximum functional coverage within shorter time duration.
Our Capabilities And Skillsets
Development of Verification Plan. (With and without tool based techniques)
Development of reusable verification environment at module, IP, Sub-system, chip or SoC level using Verification Methodologies like eRM, VMM, OVM, UVM and UVM-MS.
Development of Self-Checking Test Cases and Regression Suite.
Development of Assertion based Checkers and Protocol Monitors.
Functional and Code Coverage Analysis.
Test case execution and analysis.
Verification report generation.
Engineers at Chiplogic are equipped to provide proven and innovative solutions, to solve your verification needs.
Analysis of your existing verification environment, suggesting suitable verification techniques and provide on- the- job training on methodologies.
Language And Methodology Expertise
UVM-MS- Mixed Signal Verification techniques using Advanced Verification
Verification IPs are reusable verification modules that typically consist of bus functional models, traffic generators, protocol monitors, and functional coverage blocks. Each verification IP accelerates the development of a complete verification environment to cut down the time to first test.
ChipLogic Semi Engineers have several years of hands on experience in developing Verification IPs for various protocols and standards across multiple methodologies and disciplines. ChipLogic Semi engineers know what it takes to develop a good verification IP, which is functionally correct and integrates smoothly into any verification environment.
Our engineers are capable and have developed both customer specific and Standard VIPs.
Behaviour modelling is a vital part of the environment development as it will either be used as part of the replacement sub-block to accelerate the development and simulation cycles or as reference model to mimic the behaviour of the DUT functionalities.
ChipLogic Semi engineers know what it takes to write a faster and functionally accurate model at higher transaction level, which integrates smoothly and takes less simulation cycles to perform the behaviour of the required functionality.
The team has hands on expertise in developing digitally accurate behaviour models for both Digital and Analogue functionalities.
Test Benches and Test Suites.
Our Key Benefits
Extensive design experience, knowledge of standards, and portfolio of IPs and customer orientation help our customers bring their product faster to the market.
Provides end to end verification assurance so that the customers can focus on more critical issues like product conceptualization, architecture, features performance etc.
Enables accelerated verification of DUT with independently developed verification IP's.
Finds bugs faster there by reducing the rate of failure or re-spin.