Semiconductor IPs

Chiplogic offers portfolio of semiconductor intellectual property (IP) blocks to support Design and Verification needs for many ASIC/FPGAs designs. With several years of IP, Subsystem and SOC design experience, our team knows what it takes to develop an RTL IP and Verification IPs that can integrate smoothly into customer designs and products.

Our extensive knowledge in domain, protocols, standards & skills that we offer for developing, testing, and integrating various kind of IPs for multiple products, helps our customers quickly productize their end solutions. We create solutions as per the needs of the customer, in keeping with the best possible process to meet all targets – a fully supported IP/VIP development exercise, in minimum time frame.

Digital IP Deliverables

  • Synthesizable, configurable RTL code in Verilog HDL
  • User guide
  • UVM based testbench to demonstrate functionality of IP
  • Synthesis scripts
  • Reports – Verification, Coverage, STA

I2C IP

I2C IP Controller can be used as I2C Master or Slave IP, it is compliant to version 6.0 of spec. It supports Standard, Fast, Fast-Mode Plus, High Speed and Ultra Fast mode speeds. It supports 7-bit, 10-bit addressing and all reserved address features. Also supports data arbitration and clock synchronization.
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SATA Host Controller

Chiplogic’s SATA Host Controller IP is compliant with the SATA bus specification 3.4 and uses AHCI 1.3.1 based interface to host software. This IP implements a standard AHCI based Host Bus Adapter. It is configurable for multiple ports and has dedicated DMA as well as register set for each port. It supports configurable number of queued commands, 32-bit and 64-bit data-path and addressing, Native Command Queuing (NCQ), Notifications, Aggressive Link Power Management, Gen1, Gen2 and Gen3 Speeds, Command List Override, Partial/Slumber and DevSleep power mode. Uses AXI interface towards host and PIPE 5.1 towards PHY
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SATA Device Controller

Chiplogic’s SATA Device Controller IP is compliant with the SATA bus specification 3.4. It implements standard Protocol Layer and Link Layer over Pipe 4.1 Interface. It uses a custom programmable list processor based data interface to implement standard commands with a mechanism to extend support for vendor specific commands. Implements AXI based host interface.
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AXI VIP

The AMBA Advanced extensible Interface (AXI) 4.0/3.0 which support both Master and Slave configuration UVM VIP. It supports Configurable Multiple Outstanding Transfers (Pipeline structure), Order and Out-of-order Transfers, supports unaligned transfers, write Strobe, narrow transfers and data before address features. In advanced an exhaustive transaction log shows time-stamped transaction from each channel, this allows easy analysis and debug. This is highly flexible and configurable verification IP.
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AHB VIP

Chiplogic-AHB Verification IP supports both Master and Slave configuration for verification of designs that includes the interfaces implementing AMBA AHB specification. The VIP is fully complaint with the AMBA specification v2.0 and supports features like pipelined operation, controllable wait states, early burst termination, locked and normal transfers, both endianness, and rebuilding transactions. The VIP provides an exhaustive transaction log that shows time-stamped transactions, this allows easy analysis and debug. ChipLogic-AHB VIP is compatible with UVM 1.2 and provides an extensive SV based coverage and assertions.
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